US Patent Issued to ROHM on April 14 for "Semiconductor device including auxiliary electrode that is electrically connected to a control electrode via a second electrode layer" (Japanese Inventor)

Posted On: 2026-04-15

ALEXANDRIA, Va., April 15 -- United States Patent no. 12,604,491, issued on April 14, was assigned to ROHM Co. LTD. (Kyoto, Japan). "Semiconductor device including auxiliary electrode that is electri... Read More

US Patent Issued to ROHM on April 14 for "Semiconductor device including auxiliary electrode that is electrically connected to a control electrode via a second electrode layer" (Japanese Inventor)

Posted On: 2026-04-15

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US Patent Issued to SAMSUNG ELECTRONICS on April 14 for "Semiconductor device including an active pattern" (South Korean Inventors)

Posted On: 2026-04-15

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ALEXANDRIA, Va., April 15 -- United States Patent no. 12,604,492, issued on April 14, was assigned to SAMSUNG ELECTRONICS Co. LTD. (Suwon-si, South Korea). "Semiconductor device including an active p... Read More

US Patent Issued to SAMSUNG ELECTRONICS on April 14 for "Semiconductor device including an active pattern" (South Korean Inventors)

Posted On: 2026-04-15

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US Patent Issued to GLOBALFOUNDRIES U.S. on April 14 for "Device over patterned buried porous layer of semiconductor material" (Vermont, New York, Massachusetts Inventors)

Posted On: 2026-04-15

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ALEXANDRIA, Va., April 15 -- United States Patent no. 12,604,493, issued on April 14, was assigned to GLOBALFOUNDRIES U.S. Inc. (Malta, N.Y.). "Device over patterned buried porous layer of semiconduc... Read More

US Patent Issued to GLOBALFOUNDRIES U.S. on April 14 for "Device over patterned buried porous layer of semiconductor material" (Vermont, New York, Massachusetts Inventors)

Posted On: 2026-04-15

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US Patent Issued to Intel on April 14 for "Gate end cap and boundary placement in transistor structures for N-metal oxide semiconductor (N-MOS) performance tuning" (Oregon Inventors)

Posted On: 2026-04-15

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ALEXANDRIA, Va., April 15 -- United States Patent no. 12,604,494, issued on April 14, was assigned to Intel Corp. (Santa Clara, Calif.). "Gate end cap and boundary placement in transistor structures ... Read More

US Patent Issued to Intel on April 14 for "Gate end cap and boundary placement in transistor structures for N-metal oxide semiconductor (N-MOS) performance tuning" (Oregon Inventors)

Posted On: 2026-04-15

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US Patent Issued to Taiwan Semiconductor Manufacturing on April 14 for "Semiconductor device with multi-threshold gate structure" (Taiwanese, American, Malaysian Inventors)

Posted On: 2026-04-15

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ALEXANDRIA, Va., April 15 -- United States Patent no. 12,604,495, issued on April 14, was assigned to Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan). "Semiconductor device with multi-t... Read More

US Patent Issued to Taiwan Semiconductor Manufacturing on April 14 for "Semiconductor device with multi-threshold gate structure" (Taiwanese, American, Malaysian Inventors)

Posted On: 2026-04-15

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US Patent Issued to ROHM on April 14 for "Semiconductor device including auxiliary electrode that is electrically connected to a control electrode via a second electrode layer" (Japanese Inventor)

US Patent Issued to ROHM on April 14 for "Semiconductor device including auxiliary electrode that is electrically connected to a control electrode via a second electrode layer" (Japanese Inventor)

US Patent Issued to SAMSUNG ELECTRONICS on April 14 for "Semiconductor device including an active pattern" (South Korean Inventors)

US Patent Issued to SAMSUNG ELECTRONICS on April 14 for "Semiconductor device including an active pattern" (South Korean Inventors)

US Patent Issued to GLOBALFOUNDRIES U.S. on April 14 for "Device over patterned buried porous layer of semiconductor material" (Vermont, New York, Massachusetts Inventors)

US Patent Issued to GLOBALFOUNDRIES U.S. on April 14 for "Device over patterned buried porous layer of semiconductor material" (Vermont, New York, Massachusetts Inventors)

US Patent Issued to Intel on April 14 for "Gate end cap and boundary placement in transistor structures for N-metal oxide semiconductor (N-MOS) performance tuning" (Oregon Inventors)

US Patent Issued to Intel on April 14 for "Gate end cap and boundary placement in transistor structures for N-metal oxide semiconductor (N-MOS) performance tuning" (Oregon Inventors)

US Patent Issued to Taiwan Semiconductor Manufacturing on April 14 for "Semiconductor device with multi-threshold gate structure" (Taiwanese, American, Malaysian Inventors)

US Patent Issued to Taiwan Semiconductor Manufacturing on April 14 for "Semiconductor device with multi-threshold gate structure" (Taiwanese, American, Malaysian Inventors)